1. Field of the Invention
The present invention is directed to a phase locked loop for locking the phase of an output signal to an input signal. More particularly, the present invention is directed to a phase locked loop for varying oscillation frequency over a broad range.
A phase locked loop is used, for example, as a local oscillator for a satellite communication apparatus. It is also widely used as a frequency synthesizer and a subcarrier recovery circuit for FM stereo or a television receiver. When a phase locked loop is used as a local oscillator for a satellite communication apparatus, it requires a particularly wide band variable oscillation frequency.
2. Description of the Prior Art
An ordinary phase locked loop (hereinafter referred to as a PLL) is shown in FIG. 1. In FIG. 1, reference numeral 11 designates a phase detector, 12 designates a loop filter, 13 designates a voltage controlled oscillator (hereinafter referred to as a VCO), 14 designates a level conversion circuit, and 15 designates a frequency divider.
Operation of the PLL will be explained hereafter. An input signal and a signal (which is obtained by dividing an output signal of the VCO 13 into 1/N through a feedback loop consisting of a level conversion circuit 14 and a frequency divider 15) are input to the phase detector 11. The phase detector 11 outputs a signal depending on the phase difference of the two inputs. A control voltage of the VCO 13 can be obtained from the signal depending on the phase difference by way of the loop filter 12. Since the oscillation frequency of an output signal of the VCO 13 is controlled by a control voltage, the PLL is controlled to eliminate a phase difference between the input signal and an output signal.
The relationship between the control voltage Vc of the VCO 13 and an oscillation frequency f.sub.out of the output signal from the VCO 13 requires a wide band oscillation frequency for the output signal of the VCO 13 as shown in FIG. 2. A graph of an applied voltage (the control voltage) and capacitance variation characteristics of a variable capacitance diode of the VCO 13 is shown in FIG. 3. As shown in FIG. 3, when the applied voltage to the variable capacitance diode is low, its capacitance changes suddenly. That is, since an impedance changes suddenly, there is a high probability that the VCO 13 may stop if the applied voltage is low. If the application frequency is in the range of f.sub.L -f.sub.H and the control voltage V.sub.c is in the range of V.sub.1 -V.sub.2 as shown in FIG. 2, oscillation stops at the point where V.sub.c .ltoreq.V.sub.0. This phenomenon often occurs in a wide band oscillation VCO.
If the control voltage (applied voltage) drops due to some reason and causes the oscillation of the VCO 13 to stop, the following problem occurs in an ordinary PLL.
The frequency divider 15 is formed as a digital circuit and therefore it is provided with a circuit, in the feedback loop at the input side, for converting the analog signal from the VCO 13 into a digital signal having a predetermined level. The circuit for this purpose is connected as the level conversion circuit 14 which includes a buffer circuit. Therefore, the frequency divider 15 is connected to receive an AC signal from the VCO 13. The buffer circuit always generates high frequency noise as shown in FIG. 4A since it is an analog circuit. Accordingly, when the PLL operates normally, a problem is not generated. If, however, oscillation of the VCO 13 stops as described above, a problem occurs because the amplitude of the high frequency noise is output as a pulse signal from the frequency divider 15, as shown in FIG. 4B, due to the threshold voltage for distinguishing a high level and a low level. This pulse signal is input to the phase detector 11. Here, the signal input from the frequency divider 15 is a broad band signal having a frequency element higher than the input signal from the input terminal. Intrinsically, if oscillation of the VCO 13 stops, control is carried out to raise the frequency of the output signal for phase matching. However, even when oscillation of the VCO 13 stops, the phase detector 11 determines, due to the effect of the high frequency noise, that the signal from the frequency divider 15 has a frequency higher than that of the input signal. Accordingly, an output signal from the phase detector 11 must be controlled to raise the frequency of the output of the VCO 13 for phase matching. In contrast, an output signal from the phase detector 11 is controlled to lower the oscillation frequency of the output signal of the VCO 13 due to the operations described above. As a result, despite the fact that the control voltage V.sub.c of the VCO 13 becomes equal to or lower than V.sub.0 and oscillation stops, control is conducted to lower the frequency of the output signal of the VCO 13. Therefore, the VCO 13 is further maintained in the stop condition and cannot return to the normal operating condition.
The PLL of the prior art which has been designed for solving the above-mentioned problems is shown in FIG. 5. The elements that are like those in FIG. 1 are designated by like reference numerals. Numeral 16 designates an adder to which a voltage V.sub.B is applied to keep the control voltage V.sub.c equal to or higher than the voltage V.sub.0. Since the voltage V.sub.B is applied to the output of the loop filter 12 by the adder 16, the control voltage applied to the VCO 13 will never become lower than V.sub.0 and therefore the VCO 13 does not stop. Thus, the problems that an ordinary PLL encounters can be eliminated.
However, in the case of the PLL shown in FIG. 5, the voltage V.sub.B output from the adder 16 is supplied from any power supply provided anywhere in the system and therefore the power supply noise is superimposed onto the voltage V.sub.B. Particularly, when a large voltage dividing resistor is used, the noise amplitude becomes higher. Accordingly, noise is directly superimposed on the control voltage of the VCO 13 and therefore the output signal of the VCO 13 is greatly influenced even if the noise level is very low for the broad band VCO. In addition, the frequency characteristics of the adder 16 itself influence the parameters of the PLL and thereby it is not a rare case that the PLL characteristics deteriorate. As described above, the loop filter 12 and the VCO 13 cause problems because they are analog circuits and easily receive the influence of noise and frequency characteristics which deteriorate the characteristics of the PLL.